The present invention relates to a data output circuit and data output method and, more particularly, to a data output system which reads out data stored in a semiconductor memory onto an internal bus line and outputs the data onto an external bus line.
The data transfer amount increases in electronic devices such as an information processing apparatus which incorporates a memory device such as a semiconductor memory. Multibit apparatuses in which the number of signals (number of bits) of the memory data bus increases from conventional 8 bits or 16 bits to 32 bits or 64 bits in addition to a higher data processing speed in the circuit are put into practical use from the prototyping stage.
Along with this, measures such as an increase in power capacitance value are required to increase the supply current of the power device of a system apparatus and prevent a power supply voltage drop caused by the switching (signal change) current of an instantaneously flowing data bus signal. The memory power design in the apparatus power design becomes important more and more.
The following problems occur depending on the memory used owing to a multibit data bus signal of the memory and a higher processing speed described above.
First, switching a data signal output from the memory has high power consumption. In addition, the internal power supply voltage fluctuates upon switching. Not only devices using the same power supply but also devices not using this power supply may malfunction. Especially in a cell phone, the frequency component of fluctuations in power supply voltage may influence the radio characteristic or the like. This is because a plurality of bits are simultaneously switched due to a multibit data bus.
An example of a data output circuit in a conventional semiconductor memory will be described with reference to FIG. 10. In FIG. 10, data on a bus has n bits (n is an integer of 2 or more). That is, the width of each bus which transmits data has n bits.
A data bus signal 10i (i is 0 to n) as an output from the read amplifier of a memory (not shown) is input to a read data latch circuit 801, and latched in response to a latch signal 12. The latch output passes as a latch data bus signal 20i through an I/O (Input/Output) buffer circuit 802, and is output as output data 40i onto an external bus in response to a data output request signal 11.
The change timings of signals are represented by T91 to T96 in FIGS. 11A to 11E. In this data output circuit, if a plurality of bits in the output data 40i are simultaneously switched at timing T96, current consumption increases, and the power supply voltage fluctuates owing to a multibit data bus (this means n is larger), as described above. Fluctuations in power supply voltage appear as noise, which generates various adverse effects.